The present invention relates to a semiconductor device, and particularly to a semiconductor device having a high resistivity load and a capacitor in a static MOS random access memory.
A conventional flip-flop type static memory cell makes use of a high resistivity polycrystalline silicon as a load resistor, as shown in an equivalent circuit of FIG. 1 wherein high resistances R.sub.1, R.sub.2 and driver metal oxide semiconductor transistors (hereinafter referred to as MOS transistors) T.sub.1, T.sub.2 are connected to storage nodes N.sub.1, N.sub.2 to constitute a flip-flop type memory cell. MOS transistors T.sub.3, T.sub.4 are rendered conductive by a word line 1. Storage nodes N.sub.1, N.sub.2 are connected to bit lines 2. Therefore, the opposing data are read onto the right and left bit lines 2.
The MOS transistor has, as shown in FIG. 2, an n.sup.+ -type source or drain region 4, a gate insulator 61, and gate electrode 5, that are formed on a p.sup.- -type silicon substrate 3. Symbol Vcc denotes a power supply voltage. Such an example has been disclosed in Japanese Patent Laid-Open No. 72069/1980. With the memory cells of the above prior art, however, the following defects arise when it is attempted to reduce the cell areas in order to realize a memory having a high packaging density and a high degree of integration.
(1) High resistances R.sub.1, R.sub.2 in the equivalent circuit of FIG. 1 make use, as shown in a section view of FIG. 2, of a high resistivity polycrystalline silicon film 11 formed on an insulator 6 on a silicon substrate 3. Since both ends of the polycrystalline silicon film 11 are used as inter-connections, low value resistors 9, 91 are formed in the polycrystalline silicon due to the diffusion of impurities at a high concentration. With such a high-resistance structure, however, reduction in the length l of a high value resistor 11 induces a punch-through phenomenon. Therefore, a heavy current flows across the low value resistors 9 and 91 at both ends of the high resistivity polycrystalline silicon film, and the memory consumes electric power in increased amounts. With the conventional high-resistance structure, therefore, it is not desirable to decrease the length l, making it difficult to scale down the device. Namely, the above-mentioned high-resistance structure is not suited for highly integrated static memory cells.
(2) Ceramic materials and resin materials used for packaging the memory elements and inter-connection materials contain trace amounts of uranium U and thorium Th. As a memory cell is hit by alpha particles that are generated when the uranium U or thorium Th decays, electron-hole pairs are generated along the projected range of alpha particles and are combined with the charge stored in the storage nodes. Therefore, the data of the memory is not held any more, and is destroyed. Such a phenomenon is called soft error.
In the conventional static memory, extinction of electric charge caused by alpha particles is compensated by parasitic capacities such as pn junction capacity formed between an n.sup.+ -type diffusion layer of the drain region and a p-type substrate of the field-effect transistor and insulating film capacity such as of gate oxide film. As the area of the memory cell decreases, however, the stored electric charge is not sufficient to compensate for the extinction of electric charge caused by alpha particles. Therefore, the rate of soft error increases with the decrease in the size of the conventional static memory cells, and reliability of the memory is markedly deteriorated.